module clock_divider_50M_to_1Hz ( input wire clk_50mhz, // 50 MHz input clock input wire rst_n, // Active-low reset output reg clk_1hz // 1 Hz output clock ); // 50 MHz → 1 Hz requires division by 50,000,000 // Count from 0 to 24,999,999 (toggle) then repeat // Total cycles: 50,000,000 = 2 × 25,000,000
reg [$clog2(MAX_COUNT+1)-1:0] counter;
localparam COUNTER_MAX = 25_000_000 - 1; // 24,999,999 reg [24:0] counter; // 25 bits needed (2^25 = 33,554,432 > 25M) clock divider verilog 50 mhz 1hz
always @(posedge clk_in or negedge rst_n) begin if (!rst_n) begin counter <= 0; clk_out <= 0; end else begin if (counter == MAX_COUNT) begin counter <= 0; clk_out <= ~clk_out; end else begin counter <= counter + 1; end end end endmodule `timescale 1ns / 1ps module tb_clock_divider; module clock_divider_50M_to_1Hz ( input wire clk_50mhz
// Test sequence initial begin $dumpfile("dump.vcd"); $dumpvars(0, tb_clock_divider); // Initialize rst_n = 0; #100; // Release reset rst_n = 1; // Run for 2 seconds (simulation time) #2_000_000_000; // 2 seconds of simulation $finish; end 000 = 2 × 25