That camp is occupied almost entirely by Donald Thomas’ book, Logic Design and Verification Using SystemVerilog (Revised) .
You need to design a pipeline. You write the RTL, but you spend 80% of your time writing the testbench. This book helps you flip that ratio. That camp is occupied almost entirely by Donald
Additionally, the revised edition is still light on (Xilinx/Altera specific). This is a textbook for ASIC methodology, but 90% applies directly to high-end FPGAs. The Verdict: Buy it. Read it. Dog-ear it. If you are an early-career digital designer, Logic Design and Verification Using SystemVerilog (Revised) will cut your debug time in half. If you are a verification engineer, it will make you a better designer because you will finally understand why RTL engineers write "bad" code (and how to fix it). This book helps you flip that ratio
Having spent the last month re-reading this for a project involving a complex memory controller, I can confidently say this is not just a reference book—it is a design philosophy. The genius of Thomas’ approach is that he refuses to separate design from verification. In most curricula, you take "Digital Logic Design" and then "Verification Methodology." Thomas argues (convincingly) that you cannot design a logic block unless you know how you will prove it works . The Verdict: Buy it
