Tsmc Standard Cell - Naming Convention

[Cell Type]_[Drive]_[Vt][Special Modifier][Height/Width Code] Common examples: INVX1LVT → Inverter, drive 1, low Vt. NAND2X2HVT → 2-input NAND, drive 2, high Vt. DFFARX4RVT → D flip-flop with async reset, drive 4, regular Vt. 3.1 Base Function (Cell Type) | Code | Function | |--------|----------------------------------| | INV | Inverter | | NAND2 | 2-input NAND | | NOR2 | 2-input NOR | | AND2 | 2-input AND | | OR2 | 2-input OR | | XOR2 | 2-input XOR | | DFF | D flip-flop (rising edge) | | DFFR | DFF with asynchronous reset | | DFFS | DFF with asynchronous set | | DFFRS | DFF with both reset and set | | DLH | Latch | | AOI21 | AND-OR-invert (2+1 input) | | OAI21 | OR-AND-invert | | BUF | Buffer | | TIEH | Tie-high (VDD) | | TIEL | Tie-low (VSS) | | DELAY | Delay cell | 3.2 Drive Strength (X ) Indicates relative current drive capability (higher number = larger transistors, faster slew, higher leakage, larger area).

Older nodes (e.g., 180nm, 130nm) may use SVT (Standard Vt) instead of RVT. 3.4 Physical Variant Modifiers These indicate special layout arrangements. tsmc standard cell naming convention

| Code | Vt type | Speed | Leakage | |-------|----------------|-------|---------| | LVT | Low Vt | Fast | High | | RVT | Regular Vt | Medium| Medium | | HVT | High Vt | Slow | Low | | ULVT | Ultra-low Vt | Fastest| Highest | | ELVT | Extreme low Vt | (deprecated in some nodes) | | | Code | Vt type | Speed |

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INVX4 drives four times stronger than INVX1 . 3.3 Threshold Voltage (Vt) TSMC offers multiple Vt options to trade leakage power vs. speed. AOI21 | | Drive | X0.5

| Field | Example codes | |--------------|----------------------------------------| | Function | INV, NAND2, DFFR, AOI21 | | Drive | X0.5, X1, X2, X4, X8, X16 | | Vt | LVT, RVT, HVT, ULVT, ELVT | | Physical | _D, _P, _F, _CK, _ISO, _LS | | Track height | 6T, 7.5T, 9T (node dependent) |

| Code | Meaning | |-----------|--------------------------------------------------------| | (none) | Regular height, standard pin placement | | _D | Double-height cell (for higher drive or reduced IR drop) | | _P | Pin access optimization (better routing) | | _F | Flip-pin (mirrored for abutment) | | _CK | Clock-specific cell (low jitter) | | _ISO | Isolation cell (power gating) | | _LS | Level shifter | | _RO | Ring oscillator cell (test) | In N7, N5, N3, TSMC uses multiple metal track heights.